The present invention generally relates to semiconductor packages and more particularly to multi-layer lead frame package and method of fabrication.
Current lead frame assembly technology employs a piece of metal alloy with a plurality of unit cells, each of which receives one or a given number of dice by die attaching process;
Most commonly, metal wires, typically fabricated from gold (Au) aluminum (Al) or copper (Cu), are then bonded onto both the top pads of one or more semiconductor dies and the lead pads of the lead frame in order to deliver signal and/or power from outside of lead frame package to internal dies and vice versa.
Metal plates and/or clips connecting the dies and the lead frame have been introduced in recent years for power semiconductor packages to eliminate wire bonding process and to reduce on resistance. However, current clip/plate assembly process employs a clip attaching step which picks and drops clip(s) for each die in a one-after-another sequence. This will reduce throughput. A need exists, therefore, to provide power semiconductor packages having desired operational characteristics.